The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including, for example, a DRAM having a COM structure.
The structure of DRAM (Dynamic Random Access Memory) memory cells is divided into two types depending on the method of forming a capacitive element. One of the types is a trench type memory cell in which a capacitive element is buried in a trench formed in an Si substrate. The other type is a stack type memory cell in which a capacitive element is stacked on an upper layer of a transistor formed on a surface of an Si substrate. The structure of the stack type memory cell is roughly divided into two types, i.e., a CUB (Capacitor Under Bit-line) structure in which bit lines are located above a capacitive element, and a COB (Capacitor Over Bit-line) structure in which bit lines are located below a capacitive element (and are located above a transistor).
In the trench type memory cell, it is necessary to form a trench in the Si substrate in the vicinity of a transistor element and. to bury a capacitive element in the trench. Thus, the shape of the trench type memory cell is complicated. Further, before the capacitive element is buried in the trench after formation of a cell capacitive film in the trench, heat treatment for forming a transistor is carried out, which makes it difficult to stabilize the characteristics of the capacitive element.
In the stack type memory cell, the sectional area of the capacitive element in the lateral direction (in the horizontal direction parallel to the principal surface of the substrate) has been decreasing as the cell area has been reduced in accordance with the demand for high integration of memory cells. To offset the reduced area, the length of the capacitive element in the longitudinal direction (in the direction perpendicular to the principal surface of the substrate) has been increasing. Thus, the capacitive element having a sufficiently large capacitance value can be secured.
At this time, in the memory cells having the CUB structure, the height of a contact that connects a cell transistor, which formed on the surface of the Si substrate, to a bit line located above the capacitive element increases, which results in an increase in parasitic capacitance to be added to the bit line. Therefore, there is a limitation in increasing the length of the capacitive element in the longitudinal direction. In view of this, the memory cells having the COB structure as disclosed in, for example, Japanese Unexamined Patent Application Publication No. 2002-353334, have recently become mainstream.
During a process in which a transistor is formed on a surface of an Si substrate and a lower electrode of a capacitive element having a cylinder shape is then formed in a memory cell array area, no metal line is formed in a CMOS logic area (peripheral circuit area) in the vicinity of the memory cell array having the COB structure, while the area is filled with insulators. The metal line is disposed in a subsequent process. Accordingly, the height of a contact that connects the transistor to the metal line increases, which results in an increase in parasitic capacitance to be added to the metal line. Due to the effect of such an increase in parasitic capacitance, a delay deterioration in logic circuits in the peripheral circuit area is not negligible.
To solve such a problem, memory cells having a COM (Capacitor Over Metal) structure which is a developed form of the COB structure have recently been put into practical use. The term “COM structure” herein used refers to a structure in which a lower electrode of a capacitive element having a cylinder shape is embedded in a part of a plurality of metal line layers formed in an upper layer. In the COM structure, the metal lines are provided so as to be adjacent to the lower electrode of the capacitive element in the horizontal direction (in the direction parallel to the principal surface of the substrate).
In the COM structure, there is no need to increase the height of the area from the transistor in the peripheral circuit area to the metal line layer so that the height becomes equal to the height of the capacitive element. Accordingly, it is considered that the COM structure is effective as a structure that secures the capacitance value of each memory cell and prevents deterioration in transistor performance, and thus the COM structure will become mainstream in the future.
In addition, Japanese Unexamined Patent Application Publication No. H10-284494 discloses a technique in which a polysilicon film is disposed along a boundary portion between a memory cell array and peripheral circuits, to thereby reduce a difference in the height between the memory cell array and peripheral circuits at the boundary portion.